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INTEGRATED CIRCUITS
SA56614-XX CMOS system reset
Product data Supersedes data of 2001 Apr 24 File under Integrated Circuits, Standard Analog 2001 Jun 19
Philips Semiconductors
Philips Semiconductors
Product data
CMOS system reset
SA56614-XX
GENERAL DESCRIPTION
The SA56614-XX is a CMOS device designed to generate a reset signal for a variety of microprocessor and logic systems. Accurate reset signals are generated during momentary power interruptions, or whenever power supply voltages sag to intolerable levels. Several reset threshold versions of the device are available. A totem-pole output topology is incorporated to provide both current source and sink capability to the user. SA56614-XX is available in the SOT23-5 surface mount package.
FEATURES
* 12 VDC maximum operating voltage * Low operating voltage (0.65 V) * Totem pole CMOS output * Offered in reset thresholds of * Available in SOT23-5 surface mount package
SIMPLIFIED SYSTEM DIAGRAM
VDD 2 VDD
APPLICATIONS
2.0, 2.7, 2.8, 2.9, 3.0, 3.1, 4.2, 4.3, 4.4, 4.5, 4.6, 4.7 VDC
* Microcomputer systems * Logic systems * Battery monitoring systems * Back-up power supply circuits * Voltage detection circuits
VDD
NE56614-XX
R VOUT RESET CPU
VREF R R
1
VSS 3 VSS VSS
SL01343
Figure 1. Simplified system diagram.
2001 Jun 19
2
853-2248 26559
Philips Semiconductors
Product data
CMOS system reset
SA56614-XX
ORDERING INFORMATION
PACKAGE TYPE NUMBER SA56614-XXGW NAME SOT23-5, SOT25, SO5 DESCRIPTION plastic small outline package; 5 leads (see dimensional drawing) TEMPERATURE RANGE -40 to +85 C
NOTE: The device has twelve detection voltage options, indicated by the XX on the `Type number'. XX 20 27 28 29 30 31 42 43 44 45 46 47 DETECT VOLTAGE (Typical) 2.0 V 2.7 V 2.8 V 2.9 V 3.0 V 3.1 V 4.2 V 4.3 V 4.4 V 4.5 V 4.6 V 4.7 V
Part number marking
Each package is marked with a four letter code. The first three letters designate the product. The fourth letter, represented by `x', is a date tracking code. For example, AALB is device AAW (the SA56614-28 reset) produced in time period `B'. Part number SA56614-20 SA56614-27 SA56614-28 SA56614-29 SA56614-30 SA56614-31 SA56614-42 SA56614-43 SA56614-44 SA56614-45 SA56614-46 SA56614-47 Marking AA U x AA V x AA W x AA X x AAY x AA Z x ABAx ABBx ABCx ABDx ABEx ABFx
PIN CONFIGURATION
PIN DESCRIPTION
PIN SYMBOL VOUT VDD VSS N/C N/C DESCRIPTION Reset HIGH output. Positive supply. Ground. Negative supply. No connection. No connection. 1 2
VOUT
1
5
N/C
VDD
2
SA56614-XX
3 4
VSS
3
4
N/C
5
SL01360
Figure 2. Pin configuration.
MAXIMUM RATINGS
SYMBOL VDD VOUT IOUT Toper Tstg P Power supply voltage Output voltage Output current Operating temperature Storage temperature Power dissipation PARAMETER MIN. -0.3 - - -40 -40 - MAX. 12 VSS - 0.3 50 85 125 150 UNIT V V mA C C mW
2001 Jun 19
3
Philips Semiconductors
Product data
CMOS system reset
SA56614-XX
DC ELECTRICAL CHARACTERISTICS
Characteristics measured with Tamb = 25 C, unless otherwise specified. SYMBOL VS VS VS/T ICC IOH INDS1 INDS2 INDS3 IPDS1 IPDS2 IPDS3 PARAMETER Reset detection threshold Hysteresis Threshold voltage temperature coefficient Supply current IDS leakage current when OFF N-channel IDS output sink current 1 N-channel IDS output sink current 2 (for VS > 2.6 V) N-channel IDS output sink current 3 (for VS > 3.9 V) P-channel IDS output source current 1 (for VS < 4.0 V) P-channel IDS output source current 2 (for VS < 5.7 V) P-channel IDS output source current 3 (for VS < 5.7 V) VDD = 0 V VS + 1.0 V 0 V -40 C Tamb +85 C VDD = VS + 1.0 V VDD = VDS = 10 V VDD = 1.2 V; VDS = 0.5 V VDS = 0.5 V; VDD = 2.4 V VDS = 0.5 V; VDD = 3.6 V VDS = 0.5 V; VDD = 4.8 V VDS = 0.5 V; VDD = 6.0 V; 4.0 V < VS < 5.7 V VDS = 0.5 V; VDD = 8.4 V 3 Fig. 18 2 Fig. 17 3 Fig. 18 1 Fig. 16 CONDITIONS TEST CIRCUIT MIN. VS - 2% VS x 0.03 - - - -0.23 -1.6 -3.2 0.36 0.46 0.59 TYP. VS VS x 0.05 0.01 0.25 - -1.4 -8.3 -14.7 2.1 2.5 3.3 MAX. VS + 2% VS x 0.08 - 1.0 0.1 - - - - - - UNIT V V %/C A A mA mA mA mA mA mA
2001 Jun 19
4
Philips Semiconductors
Product data
CMOS system reset
SA56614-XX
TYPICAL PERFORMANCE CURVES
0.50 0.45 I DD, SUPPLY CURRENT (mA) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 -50 VDD = VS + 1.0 V NORMALIZED TO 25 C +0.20 +0.15 +0.10 +0.05 VS -0.05 -0.10 -0.15 -0.20 -50 VCC FALLING VS NORMALIZED TO 25 C
VS , NORMALIZED THRESHOLD (V)
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Tamb, TEMPERATURE (C)
Tamb, TEMPERATURE (C)
SL01344
SL01345
Figure 3. Supply current versus temperature.
Figure 4. Detection threshold versus temperature.
200 VS(HYS) , DETECTION HYSTERESIS (mV) VS(HYS) = VSH - VSL (VCC RISING - VCC FALLING) 150
3.0 VDS = 0.5 V I DS , OUTPUT FET CURRENT (mA) 2.5
2.0 N-CHANNEL 1.5
100
1.0 P-CHANNEL 0.5
50
0 -50
-25
0
25
50
75
100
125
0 -50
-25
0
25
50
75
100
125
Tamb, TEMPERATURE (C)
Tamb, TEMPERATURE (C)
SL01346
SL01347
Figure 5. Detection hysteresis versus temperature.
Figure 6. Output FET current versus temperature.
5.0 TAMB = 25 C TYPICAL CHARACTERISTIC. DETECTION AND RELEASE VOLTAGE POINTS DEPEND ON THE SPECIFIC DEVICE TYPE. VS(HYS) 2.0 DETECTION (VSL) RELEASE (VSH )
0.6 TAMB = 25 C 0.5 I DD , SUPPLY CURRENT ( A)
VOUT , OUTPUT VOLTAGE (V)
4.0
0.4
3.0
0.3
0.2
1.0
0.1
0 0 1.0 2 .0 3.0 4.0 5.0 6.0 VDD, SUPPLY VOLTAGE (V)
0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 VDD, SUPPLY VOLTAGE (V)
SL01348
SL01349
Figure 7. Output voltage versus supply voltage.
Figure 8. Supply current versus supply voltage.
2001 Jun 19
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Philips Semiconductors
Product data
CMOS system reset
SA56614-XX
105 t PHL, t PLH , PROPAGATION DELAY (s) TAMB = 25 C (SEE FIGURES 10 AND 11) 104 VS + 2.0 V INPUT SIGNAL 1.2 V VSS 103 tPHL
7.0 V
102 tPLH
OUTPUT SIGNAL
3.5 V
101
10-5
10-4
10-3
10-2
10-1
tPHL tPLH
VSS
CL, OUTPUT LOAD CAPACITANCE (F)
SL01350
SL01351
Figure 9. Propagation delay versus output load C.
Figure 10. Propagation delay measurements.
7.0 V
VDD
RPU = 100 k
INPUT SIGNAL
SA56614-XX
OUTPUT
VSS
CL = 10 pF to 0.1 F
VSS
SL01352
Figure 11. Propagation delay measurement circuit.
2001 Jun 19
6
Philips Semiconductors
Product data
CMOS system reset
SA56614-XX
TECHNICAL DESCRIPTION
The SA56614-XX is a CMOS device designed to monitor the system's power source and provide a system reset function in the event the supply voltage sags below an acceptable level for the system to reliably operate. The SA56614 generates a compatible reset signal for a wide variety of microprocessor and logic systems. The device can operate at voltages up to 12 volts. The series includes several versions providing precision threshold voltage reset values of 2.0, 2.7, 2.8, 2.9, 3.0, 3.1, 4.2, 4.6, and 4.7 V. The reset threshold incorporates a typical hysteresis of (VS x 0.05) volts to prevent erratic resets from being generated. The SA56614 operates at very low supply currents, typically 0.25 A, while offering a high precision of threshold detection (2%). The output of the SA56614 incorporates an active Totem-Pole output topology comprised of complimentary P-Channel and N-Channel FETs. A P-Channel FET is on the high supply side and when ON pulls the output to or near the VDD supply voltage from which output source current can be obtained. A complimentary N-Channel FET is on the low or ground side, and actively pulls the output LOW or to ground with the capability of sinking current into the output. Both devices supply system reset signals. The user should keep in mind, when connecting the SA56614 to a system, the effect of supplying source current from the output of the SA56614 on the system. This is of particular importance where the SA56614 is operated from a different supply source than the rest of the system. Figure 12 is a functional block diagram of the SA56614. The internal reference source voltage (VREF) is typically 0.8 V over the operating temperature range. The reference voltage is connected to the non-inverting input of the threshold comparator while the inverting input monitors the supply voltage through a resistor divider network made up of R1, R2, and R3. The output of the threshold comparator drives the totem-pole output stage of the device. When the supply voltage sags to the threshold detection voltage, the resistor divider network supplies a voltage to the inverting input of the threshold comparator which is less than that of VREF, causing the output of the comparator to adopt a HIGH output state. This causes the high side P-Channel FET of the Totem-Pole output stage to turn OFF while simultaneously turning the low side N-Channel FET from OFF to an active ON state, pulling the output to a LOW voltage state. The device adheres to a true input/output logic protocol. The output goes to a LOW voltage state when input is LOW (below VS) and the output HIGH goes to a HIGH voltage state when the input is HIGH (above VS). The low side N-Channel FET (TR3) establishes threshold hysteresis by turning ON whenever the threshold comparator's output goes to a HIGH state (when VDD sags to or below the threshold level). TR3's turning ON causes additional current to flow through resistors R1, and R2 causing the inverting input of the threshold comparator to be pulled even lower. For the comparator to reverse its output polarity and turn OFF TR3, the VDD source voltage must overcome this additional pull-down voltage present on the comparator's inverting input. The differential voltage required to do this establishes the hysteresis voltage of the sensed threshold voltage. Typically it is (VS x 0.05) volts. When the VDD voltage sags and is at or below the Detection Threshold (VSL), the device will assert a Reset LOW output at or very near ground potential. As the VDD voltage rises from (VDD < VSL) to VSH or higher, the reset is released and the output follows VDD. Conversely, decreases in VDD from (VDD > VSL) to VSL or lower cause the output to be pulled to ground. Hysteresis Voltage = Release Voltage - Detection Threshold Voltage VHYS = VSH - VSL where: VSH = VSL + VHYS VREF(R1 + R2) / R2 VSL = VREF(R1 + R2 + R3) / (R2 + R3) When VDD drops below the minimum operating voltage, typically less than 0.95 volts, the output is undefined and output reset low assertion is not guaranteed. At this level of VDD the output will try to rise to VDD. The VREF voltage is typically 0.8 V. The devices are fabricated using a high resistance CMOS process and utilize high resistance R1, R2, and R3 values requiring very small amounts of current. This combination achieves very efficient low power performance over the full operating temperature.
VDD
2
NE56614-XX
R1 TR1 1 R R2 TR2 VOUT
VREF
R3 VSS 3
TR3
SL01353
Figure 12. Functional diagram
2001 Jun 19
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Philips Semiconductors
Product data
CMOS system reset
SA56614-XX
TIMING DIAGRAM
The timing diagram shown in Figure 13 depicts the operation of the device. Letters A-J on the TIME axis indicate specific events. A: At `A', VDD begins to increase. Also the VOUT voltage initially increases but abruptly decreases when VDD reaches the level (approximately 0.8 V) that activates the internal bias circuitry and RESET is asserted. B: At `B', VDD reaches the threshold level of VSH. At this point the device releases the hold on the VOUT reset. The Reset output VOUT tracks VDD as it rises above VSH (assuming the reset pull-up resistor RPU is connected to VDD). In a microprocessor based system these events release the reset from the microprocessor, allowing the microprocessor to function normally. C-D: At `C', VDD begins to fall, causing VOUT to follow. VDD continues to fall until the VSL undervoltage detection threshold is reached at `D'. This causes a reset signal to be generated (VOUT Reset goes LOW). D-E: Between `D' and `E', VDD starts rising. E: At `E', VDD rises to the VSH. Once again, the device releases the hold on the VOUT reset. The Reset output VOUT tracks VDD as it rises above VSH. F-G: At `F', VDD is above the upper threshold and begins to fall, causing VOUT to follow it. As long as VDD remains above the VSH, no reset signal will be triggered. Before VDD falls to the VSH, it begins to rise, causing VOUT to follow it. At `G', VDD returns to normal. H: At event `H' VDD falls until the VSL undervoltage detection threshold point is reached. At this level, a RESET signal is generated and VOUT goes LOW. J: At `J' the VDD voltage has decreased until normal internal circuit bias is unable to maintain a VOUT reset. As a result, VDD may rise to less than 0.8 V. As VDD decreases further, VOUT reset also decreases to zero.
VS VSH VSL VDD
0
VOUT
0 A B C D E TIME F G H J
SL01354
Figure 13. Timing diagram.
2001 Jun 19
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Philips Semiconductors
Product data
CMOS system reset
SA56614-XX
APPLICATION INFORMATION
VDD VDD CPU A R11 CURRENT CHANGES
SA56614-XX
VOUT
VDD
RESET
VSUPPLY R12
SA56614-XX
VSS
OUTPUT
VSS GND
SL01355 SL01356
Figure 14. Conventional reset application Small changes in supply current will occur when the SA56614 asserts or releases a reset. In some cases this can cause oscillations of the device. This can present a problem, particularly where high impedance VDD sources are employed. Figure 15 shows how this may occur.
Figure 15. High impedance supply operating problems Significant voltage variations of VDD may occur when the device is operated from high impedance power sources. When the device asserts or releases a reset, VDD variations are produced as a result of the voltage drop developed across R11 due to the current variations through the resistor R11 (representing the supply impedance). If the VDD variations are large, such that they exceed the Detection Hysteresis, the output of the device can oscillate from a HIGH state to a LOW state. The user should avoid using high impedance VDD sources to prevent such situations.
2001 Jun 19
9
Philips Semiconductors
Product data
CMOS system reset
SA56614-XX
TEST CIRCUITS
A VDD RPU 100 k
VDD
V
SA56614-XX
VSS
VOUT
SL01357
Figure 16. Test Circuit 1
VDD
VDD
V
SA56614-XX
VSS
A VOUT V VDS
SL01358
Figure 17. Test Circuit 2
VDD V VDD V
VDS A
SA56614-XX
VSS
VOUT
SL01359
Figure 18. Test Circuit 3
2001 Jun 19
10
Philips Semiconductors
Product data
CMOS system reset
SA56614-XX
PACKING METHOD
GUARD BAND
TAPE REEL ASSEMBLY
TAPE DETAIL
COVER TAPE
CARRIER TAPE
BARCODE LABEL
BOX
SL01305
Figure 19. Tape and reel packing method
2001 Jun 19
11
Philips Semiconductors
Product data
CMOS system reset
SA56614-XX
SOT23-5: plastic small outline package; 5 leads; body width 1.5 mm
1.35
1.2 1.0
0.025
0.55 0.41
0.22 0.08
3.00 2.70
1.70 1.50
0.55 0.35
2001 Jun 19
12
Philips Semiconductors
Product data
CMOS system reset
SA56614-XX
NOTES
2001 Jun 19
13
Philips Semiconductors
Product data
CMOS system reset
SA56614-XX
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Date of release: 06-01 Document order number: 9397 750 08453
Philips Semiconductors
2001 Jun 19 14

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